1. Field of the Invention
The present invention relates to image sensors and arrays of image sensors. More particularly, the present invention relates to compressive CMOS image sensors and image sensor arrays for still camera and other applications and to methods for operating those arrays.
2. The Prior Art
Integrated image sensors are known in the art. Such sensors have been fabricated from charge-coupled devices (CCDs) and as bipolar and MOS image sensors.
A problem encountered with prior-art imagers is a limitation on the dynamic range of images that can be captured by the array. Images that contain both low-light-level pixels and high-light-level pixels could be improved if the dynamic range of the imager could be increased.
In an active pixel sensor, the sensitivity of measuring charges generated by photons can be described as a charge-to-voltage gain. Typically, in a prior art active pixel sensor, the charge-to-voltage gain is accounted for by two factors. A first factor is the reciprocal of the capacitance of the charge accumulation node in the sensor where photocharge accumulates to change a potential (a reciprocal capacitance represents units of volts per coulomb). A second factor is the gain of the readout amplifier, typically less than one using a source follower. Voltage dependence of the photodiode capacitance and other capacitances, and nonlinearities of the readout amplifier transistor can make the gain vary with level, so that the overall transfer curve may be somewhat nonlinear. A nonlinearity in which higher light intensities give lower gains is said to be compressive. A significant degree of compressive nonlinearity can have a beneficial effect on the signal-to-noise ratio of the image at low light levels, and can thereby enhance the usable dynamic range of the imager.
It is therefore an object of the present invention to provide a pixel sensor and an array of pixel sensors that overcome some of the shortcomings of the prior art.
A further object of the present invention is to provide a storage pixel sensor and an imaging array of storage pixel sensors that includes image level compression.
Another object of the present invention is to provide a storage pixel sensor and an imaging array of storage pixel sensors that includes multi-breakpoint image level compression.
A pixel sensor with compression according to the present invention comprises a photosensor coupled to a nonlinear capacitor arranged to have a compressive photocharge-to-voltage gain function. An amplifier having an input and an output is coupled to the nonlinear capacitor. According to one embodiment of the invention, the nonlinear capacitor comprises a MOS capacitor including a first plate formed from a channel region in a semiconductor substrate and having a diffusion terminal coupled to the photosensor, and a second plate formed from a gate material coupled to an adjustable voltage source. According to another embodiment of the invention, the compressive photocharge-to-voltage gain function of the pixel sensor has more than one breakpoint.
According to another embodiment of the invention, a pixel sensor according to the present invention disposed on a semiconductor substrate comprises a MOS capacitive element having a gate terminal coupled to an adjustable potential and a diffusion terminal. A photodiode has a first terminal coupled to a first potential (ground) and a second terminal coupled to the diffusion terminal of the MOS capacitive element. A semiconductor reset switch has a first terminal coupled to the second terminal of the photodiode and a second terminal coupled to a reset reference potential that reverse biases the photodiode. A semiconductor amplifier has an input coupled to the diffusion terminal of the MOS capacitive element and an output. The semiconductor reset switch has a control element coupled to a control circuit for selectively activating the semiconductor reset switch.
A first storage pixel sensor according to the present invention disposed on a semiconductor substrate comprises a MOS capacitive element having a gate terminal coupled to an adjustable potential and a diffusion terminal. A photodiode has a first terminal coupled to a first potential (ground) and a second terminal coupled to the diffusion terminal of the MOS capacitive element. A semiconductor reset switch has a first terminal coupled to the second terminal of the photodiode and a second terminal coupled to a reset reference potential that reverse biases the photodiode. A semiconductor transfer switch has a first terminal coupled to the diffusion terminal of the MOS capacitive element. A semiconductor amplifier has an input coupled to the second terminal of the semiconductor transfer switch and an output. A semiconductor row-select switch has a first terminal coupled to the output of the semiconductor amplifier, a second main terminal coupled to a column output line and a control element coupled to a row-select line. The semiconductor reset switch and the semiconductor transfer switch each have a control element coupled to a control circuit for selectively activating the semiconductor reset switch and the semiconductor transfer switch.
A second storage pixel sensor according to the present invention disposed on a semiconductor substrate comprises a MOS capacitive storage element having a gate terminal coupled to an adjustable potential and a diffusion terminal. A photodiode has a first terminal coupled to a first potential (ground) and a second terminal. A semiconductor reset switch has a first terminal coupled to the second terminal of the photodiode and a second terminal coupled to a reset reference potential that reverse biases the photodiode. A semiconductor transfer switch has a first terminal coupled to the second terminal of the photodiode and a second terminal coupled to the diffusion terminal of the MOS capacitive storage element. A semiconductor amplifier has an input coupled to the diffusion terminal of the MOS capacitive storage element and an output. A semiconductor row-select switch has a first terminal coupled to the output of the semiconductor amplifier, a second main terminal coupled to a column output line and a control element coupled to a row-select line. The semiconductor reset switch and the semiconductor transfer switch each have a control element coupled to a control circuit for selectively activating the semiconductor reset switch and the semiconductor transfer switch.
In all of the embodiments of the present invention, the adjustable potential to which the gate terminal of the MOS capacitive element is coupled is capable of supplying between about 1 and 3 volts. Depending on the process technology, higher voltages may be used as well.
According to presently preferred storage pixel embodiments of the invention, a light shield is disposed over portions of the semiconductor substrate including the storage node and the connection of the storage switch to the amplifier.
In addition, means are preferably provided for preventing substantially all minority carriers generated in the semiconductor substrate from entering the storage node.